Verification tools and methodologies have both evolved and undergone revolutionary
changes, and both are equally as important. Without a doubt, simulators and support
tools have evolved to keep pace with the incremental requirements (primarily increasing
design size). However, it is the revolutions that provide the significant increase in
productivity necessary to stay abreast of Moore’s Law. While the hoopla around
Moore’s Law has traditionally been around advances in semiconductor technology, it is
worth noting that whatever you build or want to build has to be verified (unless of course
all you are going to build is memory).
Complex designs can be implemented with a divide and conquer approach – and of
course by deploying more designers. Verification, on the other hand, must deal with the
large designs (often extremely large) as a whole for which the burden primarily falls on
the underlying verification tools and associated methodologies. These tools must be able
to ‘simulate’ a model of the design, often at different levels of abstraction (register
transfer level, gate, etc.). Fortunately, assertion-based verification enables a
revolutionary methodology change that addresses this burden through enhanced
observability (result checking) and testing (development of actual tests).
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Editorial
Upcoming Events
DAC 2012 at San Francisco CA - Jun 3 - 7, 2012
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