Faced with increasing design complexity, growing IC capacity, mounting cost, escalating risk, stagnant-maybe even declining-engineering productivity, and shrinking time-to-market, our industry as a whole is rallying around advanced design, verification and debug languages. These languages build on the experiences and lessons of the past, integrate recent successes, and open the door to innovative design, verification, and debug practices. SystemVerilog is one such example of a language that builds on Verilog-2001, folds formerly proprietary test generation facilities found only in testbench languages such as Vera and Temporal e [12], and makes a leap forward by also including response-monitoring capabilities of assertions from temporal OVA and PSL. PSL itself comes primarily from Sugar but also combines numerous concepts and input from the developers of ForSpec [3], Temporal e, and CBV [7]. The potential of SystemVerilog is not merely in its impressive host of useful elements, but also lies in the benefits of a unifying coherent framework for a comprehensive design, verification, and debug methodology. The language adds design abstraction, data encapsulation, flexibility and reuse, revamped syntax and semantics, and numerous facilities for productivity enhancements. We overview here several key elements of SystemVerilog focusing on their design and debug aspects; the challenges and the opportunities they pose.
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Editorial
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DAC 2012 at San Francisco CA - Jun 3 - 7, 2012
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