As multi-core SoCs continue to evolve, their interconnect architectures have become the major design challenge. Implementing Quality of Service (QoS) in order to share access to tightly-coupled memories; coordinating error detection and handle protocols; debugging data flow for concurrent processors; as well as fundamental challenges such as SoC timing closure are all effected by the level of interoperability the interconnect provides between IP cores and external memory..
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Editorial
Upcoming Events
DAC 2012 at San Francisco CA - Jun 3 - 7, 2012
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