Computer and storage systems contain many printed circuit boards that utilize common pieces of logic
and technology. New technologies are signaling faster, with increased edge rate, clocking off both
edges, leading to reduced system level timing and noise margins. The reuse of signal integrity and
timing analysis environments with their associated models results in significant savings in manpower
and schedule. This paper explores the key aspects in Design Analysis Reuse methodology. This includes
exploring the types of data that must be portable between designs and how mechanical changes to the
PCB design can be handled without loss of reuse. Reuse within a design as well as between designs is
discussed.
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