USB 3.0 is rapidly being adopted by a growing number of system level companies, spawning many integrated device manufacturers (IDMs) to develop new chips to address this need. USB 3.0 supports data transfer rates up to 4.2 Gbits/sec, creating new challenges for IC package designers and signal integrity engineers that must be addressed as part of the high-speed SERDES design process. These higher data rates will require substantially improved modeling accuracy of the IC package’s interconnect, wire bonds, vias, and solder balls that are part of such high-speed data paths.
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Editorial
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DAC 2012 at San Francisco CA - Jun 3 - 7, 2012
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