Clock recovery loop behavior can seriously affect the performance of a high-speed
serial channel and yet the only data that is generally available
is that which is inferred through jitter tolerance testing for a small number of
channels.
This paper introduces a method for extracting the jitter transfer function,
jitter tolerance and pattern dependent jitter from an IBIS-AMI model under
realistic channel conditions, and presents example results from a generic
bang-bang clock recovery design and seven commercial SerDes designs.
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Editorial
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