Successful high-speed design achieves system timing closure by balancing static timing and
signal integrity analysis against decisions made during the design process. A high speed design
methodology should allow the designer to determine how design tradeoffs affect both system
timing margins and signal integrity performance.
This paper outlines a rigorous, repeatable methodology for approaching high speed design and
shows how HSPICE-based signal integrity analyses fit within that process. We use a DDR2
memory example to illustrate the different signal integrity analyses that must be performed using
HSPICE.
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Editorial
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DAC 2012 at San Francisco CA - Jun 3 - 7, 2012
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