One of the most significant challenges in Electronic Design Automation (EDA) is the reuse of design analysis and
simulation data for a family of co-developed chip sets. Design teams must reconstruct data libraries for each
system even though the same basic bus structures are used. This library reconstruction is due to issues such as
assorted form factors, chip set variations, board partitioning, and multiple configurations of processors, memory and
peripherals. Current approaches are time consuming and error prone, and require significant amount of scarce
signal integrity engineering talent.
|
Editorial
Upcoming Events
DAC 2012 at San Francisco CA - Jun 3 - 7, 2012
|
|
|
