[SoC] SoCcentral Online Articles, March 14, 2005
On-chip power integrity effects and their influence on the entire power delivery system have become a major concern in the design of large and complex high-speed SoC designs. Today's extreme design challenges require a complete power-aware solution that encompasses the global effects of the entire power delivery system, including the realistic effects of the package and the PC board on the functional operation of the IC. Written by Dr. Fang and John Kane.
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