The method of three-dimensional I/O power modeling will be reviewed in detail based on the learning from the
previous one-dimensional and two-dimensional models. This paper will cover the latest development of next generation
microprocessor I/O power models and the adoption of a new three-dimensional modeling methodology to meet the
challenging design requirements of a high performance signal bus with short turn-around times. The paper also presents
a new technique of using damping resistors to attenuate the high frequency noise on the IO supply.
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Editorial
Upcoming Events
DAC 2012 at San Francisco CA - Jun 3 - 7, 2012
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