Just as floorplanning has become vital to the success of SoC design, package-aware I/O planning is essential for meeting cost, time-to-market and performance targets. Without such planning, excessive package complexity can significantly increase product cost—often pushing a chip’s package cost higher than the cost of its silicon. Additionally, I/O problems may limit performance and go undetected until verification; the numerous design cycles required to correct the problems may delay time to market by weeks. Even without such problems, the traditional I/O design methodology adds weeks to SoC design schedules.
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Editorial
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DAC 2012 at San Francisco CA - Jun 3 - 7, 2012
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