Featured Paper by Nghi Huynh, Lavanya Murugesan
Often underestimated in the initial stages of physical design, routing congestion can pose a
severe threat to successful design implementation. Migration towards 90-nanometer (nm) and
65-nm technologies, integration of multiple intellectual properties (IP), increased complexity of
application specific integrated circuits (ASIC) designs, and small die size requirements can
directly affect routing performance. Careful up-front planning is a must to avoid congestion and
routing issues. A �correct-by-construction� approach to routability becomes a gating factor for
successful design completion.
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Editorial
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DAC 2012 at San Francisco CA - Jun 3 - 7, 2012
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