Each smaller sub-micron process technology brings a new set of physical problems for IC designers. Among the toughest of these problems are meeting electrical parasitic constraints and minimizing signal integrity issues in the interconnect routing while still reaching routing completion, controlling power consumption, staying within the specified die-size and speeding time to market. For digital designs, some of these concerns are addressed by automatic place and route tools. However, for custom IC
designs, these issues remain largely unaddressed due to the inadequacy of the
automation tools.
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Editorial
Upcoming Events
DAC 2012 at San Francisco CA - Jun 3 - 7, 2012
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