Higher integration densities, smaller feature lengths, and other technology advances, as well as architectural evolution, have made microprocessor cores exceptionally complex. Currently, Software-Based Self-Test (SBST) is becoming an attractive test solution since it guarantees high fault coverage figures, runs at-speed, and matches core test requirements while exploiting low-cost ATEs. However, automatically generating test programs is still an open problem. This paper presents a novel approach for test program generation, that cou-ples evolutionary techniques with hardware acceleration. The methodology was evaluated targeting a 5-stage pipelined processor implementing a SPARCv8 microprocessor core.
|
Editorial
Upcoming Events
DAC 2012 at San Francisco CA - Jun 3 - 7, 2012
|
|
|
