Featured Paper by Arvind Shenoy, Deepak N, Raghavendra KS
This paper describes a near at-speed BIST for Dual Port Embedded SRAMs. A new synthesis
methodology has been proposed for achieving near at-speed BIST with isolated memory, without
compromising much on area. In addition, two to three fold improvement in BIST frequency is
possible by using new synthesis methodology. Synopsys DC has been used for synthesis of BIST
Logic.
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Editorial
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DAC 2012 at San Francisco CA - Jun 3 - 7, 2012
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