Software simulation is the primary method used to verify logic in integrated circuit (IC) designs. When simulation discovers logic errors through unexpected logical behavior, users must trace the causes. This tracing requires that logic values be recorded during simulation. For large designs, recording these values adds enormous overhead to the simulation process. This causes users to adopt a variety of costly strategies for reducing this overhead. New Visibility Enhancement technology enables methodologies that reduce the need for this manual effort and improves the overall productivity of logic verification with simulation. This technology identifies a minimal subset of signals required for full visibility and automatically expands the data for other signals from this recorded subset during debug.
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Editorial
Upcoming Events
DAC 2012 at San Francisco CA - Jun 3 - 7, 2012
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