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System-on-Chip (SoC) designs are becoming increasingly complex. Modelling, verification, and debug facilities at RTL have become quite inadequate in the face of rising design challenges. Transaction-Level Models (TLM) described at the top levels of design, and/or extracted from the design implementation promises to not only speed-up verification but also ease design understanding, evaluation and analysis thus alleviating the design burdens at the SoC level. We present here our research and development efforts in the development of multi-level adaptors and transformers, as well as analysis, visualization, and debug facilities that revolve around TLM and the opportunities it affords for cooperative development among architect and design teams.
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