Featured Paper by Sverre Wichlund
Today’s new process technologies become progressively more complex. As this is combined
with steadily increasing design sizes, the result is a dramatic increase in the number of scan test
vectors that must be applied during manufacturing test. This in turn may result in costly tester
reloads and unacceptable test application times. During the last few years, substantial research
has been put into techniques to tackle this problem [1-7]. In this paper we investigate the
usefulness of the so-called Illinois-scan architecture [8,9] on a 3Mgate design. We also devise a
‘X’ tolerant space compaction scheme which is diagnosis friendly. The latter is important when it
comes to maintain throughput on the test floor [10,11]. By utilizing the shared scan-in feature of
DFT Compiler and TetraMAX as well as the internal-pins flow in DFT Compiler we were able to
reduce the scan test time and data volume by a factor 7.8 and 6.6 accordingly, with very little
area overhead (less than 0.2%). This saved us from running into a real tester memory bottleneck.
Keywords: DFT, Illinois-scan, BIST, compaction, ATE.
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