Featured Paper by Wei-Si Jiang
Static timing analysis (STA) with process-voltage-temperature (PVT) corner models has widely
been used in IC designs. As deep and ultra-deep submicron technologies have become the main
stream in the IC industry, it is getting more and more crucial for STA to reduce pessimism. This
paper will describe how the advanced features, introduced in the recent versions of
PrimeTime(PT), such as path-specific timing analysis, location-aware on chip variation(LOCV)
analysis, net-specific timing derate setting, net-specific parasitic scaling, etc., greatly helped
National's CAD organization and product line designers
in establishing a new and better STA flow with timing results closer to silicon reality. The paper
will also share National's experience on how these advanced features were used for silicon
debugging to pinpoint the origins of silicon failures and/or to identify weak spots responsible for
low yield. The paper will discuss two 0.13um designs at National in detail to show the
effectiveness as well as limitations of our approach..
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Editorial
Upcoming Events
DAC 2012 at San Francisco CA - Jun 3 - 7, 2012
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