Featured Paper by Ravi Kumar Satzoda, Chip-Hong Chang and Thambipillai Srikanthan
Dynamic power simulation is always a complicated issue as it depends on the switching activity
of the nodes in the circuit. Since the switching activities can be determined by providing actual
input stimuli to the circuit, a common question that always arises is the number and type of input
vectors used for simulation. This paper introduces Monte Carlo statistical analysis for dynamic
power simulation for RTL designs using Synopsys Power Compiler. The proposed methodology
helps to determine the confidence level and error with which a set of N input vectors would
result in a dynamic power P that is consumed by the design. It is based on the switching activity
of the circuit at different simulation times. This method has been previously used for designs at
transistor level in HSPICE. We propose this methodology at higher abstraction levels for RTL
designs. Experimentation on RTL designs using Synopsys Power Compiler indicates converging
trends in the dynamic power dissipation as simulation time progress which is suggested in
literature. We present this preliminary study on RTL descriptions. It needs further analysis and
experimentation to determine the accuracy of the power simulation results using this
methodology at different levels of circuit description. Also, the accuracy of the results using this
statistical method needs to be verified against the actual power consumption of the chip after
fabrication.
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