This TecForum begins by providing background on existing methods employed by full-custom
designers for multi-gigahertz clocks. In addition, it explores in some detail the inductive nature of GHz
clock networks. A novel clocking methodology termed "rotary clocking" will be proposed that provides:
near zero skew; greatly reduced noise generation; insensitivity to process, voltage and temperature
variations; and very significant power savings. The presenters provide evidence that this method would
allow ASIC and COT designers to utilize far more of the available process performance, narrowing the
gap to full-custom performance. The TecForum will conclude with a look at additional tools and
techniques that need to be developed to fully automate this approach.
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Editorial
Upcoming Events
DAC 2012 at San Francisco CA - Jun 3 - 7, 2012
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