The first silicon measurements of a 3.5GHz fully pipelined
dynamic logic family that utilizes only NMOS devices in a 0.25ìm
SOI process are presented. A key feature of the test-chip involves
the use of the rotary traveling wave oscillator (RTWO) [1, 2, 3, 4]
as clock and power source for the logic family. This oscillator
topology has previously been demonstrated in a variety of
processes and frequency ranges including a 36GHz low-phasenoise
oscillator in 0.13ìm CMOS [5].
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Editorial
Upcoming Events
DAC 2012 at San Francisco CA - Jun 3 - 7, 2012
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