All Categories : Technical Presentations Bookmark and Share

Title : Design and Verification without Constraints for System on Chip
Company : MindTree Ltd
Date : 16-Feb-2010
Downloads : 9

Rate This File
5 Stars
4 Stars
3 Stars
2 Stars
1 Star

We propose a new methodology flow which will allow the visual definition of a complex SoC through instantiation of parametric IP such as processors, SDRAM controllers, DMA engines, on-chip buses, peripherals, switch matrices and coherency directories, coprocessors, etc. Script based automation helps in integrating any IP with any configurations ,selects relevant and corresponding Verification IPs(in-house developed-if Design IPs are standard), uses suitable Bus Wrappers(OCP,EBI,Avalon,MicroBlaze,PicoBlaze,PIF,AXI,AHB,APB,Generic and others) and stitches all the components design as well verification(synthesizable testbench components ) together and making use of TLMs,BFM (replacing CPUs with Master BFMs) or Process Core based designs creates an CSOC environment. The framework reduces the time to build integration and verify the functionality-it also has the complete set up from assembler to DFT.
User Reviews More Reviews Review This File

True Circuits:

Featured Video
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Reverie: All That Glitters is not Past
More Editorial  
Digital and FPGA Hardware Designer for Giga-tronics Incorporated at San Ramon, CA
Technical Support Engineer for EDA Careers at Freemont, CA
Technical Marketing Manager Valley for EDA Careers at San Jose, CA
SoC Design Engineer for Intel at Santa Clara, CA
Senior Physical Design Engineer for Ambiq Micro at Austin, TX
Upcoming Events
European 3D Summit 2017 at 3, parvis Louis Néel 38054 Grenoble France - Jan 23 - 25, 2017
3D Printing Electronics Conference at High Tech Campus 1, 5656 Eindhoven Eindhoven Netherlands - Jan 24, 2017
DesignCon 2017 at Santa Clara Convention Center Santa Clara CA - Jan 31 - 2, 2017
Embedded Neural Network Summit at San Jose CA - Feb 1, 2017
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: UltraPLL

Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy