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Title : Survey of Chip Designers on the Value of Formal Verification Across the Spectrum of Applications
Company : Jasper Design Automation
Date : 16-Jul-2010
Downloads : 10

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Over 50 engineers and engineering managers were surveyed at DAC 2009 by Jasper Design Automation as part of a market research and analysis program examining how designers use formal verification across the design cycle. Within eight application areas, respondents indicated which formal technology applications are most interesting and valuable, all the way down to each detailed engineering task within the application areas, and their hierarchy of value. The set of applications used in the survey are current uses of JasperGold and ActiveDesign, as developed by Jasper Design Automation and its customers.
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