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Title : Modeling and Verifying Cache-Coherent Protocols, VIP, and Designs: Jasper and ARM Bolster ACE Protocol Deliverables
Company : Jasper Design Automation
File Name : Modeling and Verifying Cache-Coherent Protocols and VIP and RTL_Jun2011.pdf
Size : 1416147
Type : application/pdf
Date : 09-Jun-2011
Downloads : 54

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This paper describes a novel method for modeling and verifying cache-coherent protocols using Jasper ActiveModel™ technology. The methodology and benefits of using ActiveModel technology to model and verify the ARM AMBA® AXI Coherency Extensions (ACE™) protocol are outlined. In addition, it describes how an ActiveModel protocol model becomes a valuable piece of system-level verification intellectual property (VIP) used to verify RTL designs. Finally, the collaboration between ARM and Jasper that resulted in the development of the interface-level VIP needed to verify RTL designs supporting the ACE protocol are detailed.
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