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Featured Paper by Kok Tiong Tee, Aan Chien Tan Conventional techniques in Static Timing Analysis relies on defining clocks to constraint all possible timing paths, and creating timing exceptions to disposition violations which could be false paths or are non timing critical for the operation under analysis. However under certain circumstances timing checks are required only on a section of the entire design, and by using the existing method whereby the Primetime tool performed timing checks to all logic paths, created redundancy in runtime and inefficiency in compute resources utilization. This paper presents an inverse method to perform static timing analysis on a targeted logic cluster by reducing unneeded gate-level netlist and SDF using ILM approach, prior to running Primetime. The paper also outlines the results on the runtime improvement based-on different logic cones extraction techniques and how this innovative approach enabled the multiple PV scenarios in one pass timing verification.
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