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Featured Paper by Duane Galbi, Ranji Loboprabhu, David Lewis In order to reduce the power of a SOC, both the DC leakage current and the active current needs to addressed. High performance cell libraries typically offer a selection of cell families which allow the designer to make a trade-off between leakage current and cell performance; whereas, active current can be reduced with the inclusion of clock gating. Power compiler offers solutions to both these issues. We will discuss the use of Power Compiler to reduce both the active and leakage current of a 90nm SOC, and compare and benchmark different strategies for leakage power reduction.
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