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Featured Paper by Lim, Jin Sean, Liu, Chin Foon With the shift in emphasis to power consumption, power estimation is becoming increasingly important during the design phase. Classical SPICE simulators are limited by capacity and speed, thus limiting the feasibility of using a classical SPICE simulator for power estimation efforts. This paper describes the Nanosim-based methodology/flow in estimating the power consumption of an interface. The paper will address the technologies used in fast-spice simulators and the trade offs between accuracy and simulation speed we can achieve using Nanosim. This methodology has enabled power estimation within 10% of the measured value to be achieved with 20x faster runtime compared to using the traditional SPICE simulator.
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