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Featured Paper by Woong Hwan Ryu, Min Wang As PCB interconnection density and channel data rate are getting increasingly higher, various 3D effects, crosstalk, and discontinuity-induced ISI are playing a much more important role, for both signal channels and power distribution networks. In particular, noise coupling between signal trace and power delivery network has become a key issue and performance limiter for high-speed chip-to-chip interface, which must be addressed appropriately. Understanding these combined signal integrity (SI) and power integrity (PI) issues in the era of gigahertz data rates requires advanced co-design methodology for SI and PI analysis. In this paper, a robust co-design methodology is established and successfully demonstrated through two case studies: investigations of DDR2-800 control bus resonance problem and DDR2-667 Vref bus noise issue. With traditional signal integrity simulations which consider an ideal power delivery system; these issues may not be observable until the post-silicon validation stage.
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