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Featured Paper by Amjad Qadan, Matt Stefaniw, Terry Biggs A continued challenge of hierarchical design is the timing budget constraint generation process. Currently available budgeting solutions tend to have long run times and provide questionable results. Additionally, they are linked to specific tools in the flow and are fairly inflexible. HP�s Systems VLSI Labs has developed a budgeting constraint generation methodology that is based on post-processing PrimeTime outputs. The result is a methodology that is extremely flexible, including the various tool flows and algorithms that may be used to generate the budget. This paper will provide an in depth description of that budgeting strategy.
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