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As gate counts continue to swell at a rapid pace, modern systems-on-chip (SoCs) increasingly are integrating more design-for-testability (DFT) capabilities. Test and diagnosis of complex integrated circuits (ICs) will soon become the next bottleneck, if, in fact, they have not already. With up to 30% of a project’s cycle already being spent debugging silicon, and typically 30–50% of total project costs being spent on test, DFT quickly is becoming the next wild card. As daunting a task as reining in all the variables related to DFT infrastructure can seem, an enormous opportunity awaits those ready to take up the challenge.
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