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Featured Paper by Joachim Geishauser, Daniel Hoheisel, Yijing Liu, Terry Gong With the increasing computation and throughput requirements of today’s System-on-Chip designs the verification of these designs becomes an even more complicated task. Multiple cores along with DMA engines need to be designed and to be integrated into the final design to build up differentiating products. Verification languages provide features to ease the job of verification, however without a methodology around them the verification task will become a nightmare. The methodology presented in this paper is demonstrating an example of a SoC verification including problem analysis, cutting down the problems into manageable tasks and utilizating the features of Vera. The paper will describe infrastructure such as the generic DMA model and a verification process for a DMA engine as well as the verification of a DMA capable peripheral. On the SoC level we will show how this approach addresses the verification problem in a reusable way.
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