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In February 2001 a new version of the VHDL Initiative Toward ASIC Modeling (VITAL) became official. VITAL 2000 includes many improvements over its predecessor, VITAL 95. However, the most dramatic change is the addition of the VITAL memory package. This package approximately doubles the number of lines of code in the VITAL packages. It provides special table formats, path delays and, timing checks for memories as well as optimized storage for memory arrays. In this paper I examine how the new package can be used to model a generic SRAM. The model is contrasted with one of identical functionality written without the package. Then the two models are compared for memory usage and simulation speed.
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