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This paper discusses the integration of SystemVerilog Assertions (SVA) into a flow that starts from a high-level executable specification and finally yields a synthesizable VHDL implementation. The test-case for our investigation is a protocol and control intensive block, taken from an application in the digital satellite broadcasting domain. It has been chosen, because assertions are especially well suited for interface and protocol checking. A cycle-accurate algorithmic VHDL model serves as high-level executable specification. Assertions are added to this model, where implementation, debugging and simulation is carried out using VCS and DVE. These assertions are then re-used to assist the HDL designer during the task of implementing the RTL design. Finally, the assertions are used to validate the synthesizable design re-using the existing test environment of the cycle-accurate model. Often, the proposed strategy for assertions is to have the RTL designer write the assertions and using it for debugging the design. Here, we try to supply the hardware engineer with a set of assertions that he can use as guidance during his design work.
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