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Featured Paper by Peter H Chen, Peter Pong, KC Wu, YW Chen, Alvin Chen, YC Chu, JJ Huang, Jim Wang This paper proposes a fast methodology to characterize Setup/Hold Time for analog IPs. Partial circuits of clock and data paths are simulated instead of the simulation of entire IPs. The partial circuits include all those paths of clock pin and data input pins before reaching the DFF. This methodology includes algorithms for multi-path searching of hierarchical SPICE netlist for the path of clock and input pins, so as to reduce the circuit subset, merge the paths of clock vs. corresponding input pins, and then characterize the setup/hold time for an analog IP. The paths of input pins and clock before DFF are used for Setup/Hold Time Characterization. The results show the accuracy of partial path extraction of circuits is 100% as in full chip simulation, while the run time is cut from 3-8 hours to within seconds.
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