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Moore’s law continues to drive both chip complexity and performance to new highs every year, and continues to stress and periodically “break” existing design flows. Fortunately for EDA users, the same shrinking geometries that make their design problems tougher are also helping to improve the performance for their EDA tools. But when it comes to functional verification, traditionally the largest bottleneck in the design process, software-based approaches like simulation continue to lose ground. Why isn’t simulation speed keeping pace with device complexity? Because many new devices like 3G cell phones, internet routers, image processors, etc. require massive verification sequences that would take many CPU-years to simulate on even the fastest PC. These sequences are often a result of the need to run long, contiguous, serial protocol streams or complex embedded software in order to fully verify a new SoC or system design. Increasingly, embedded software is overtaking the hardware content of SoC devices. The net result is a kind of chicken-egg problem: which comes first - the “final” hardware or the “final” software? Embedded software developers need an accurate model of the hardware in order to validate their code, while the hardware designers need fairly complete software to fully validate their ASIC or SoC. Software developers can sometimes get started using a bare-bones, non-cycle accurate high-level C model of the processor or an instruction set simulator (ISS). Similarly, chip designers can simulate their design along with small code snippets or diagnostics to verify basic functionality. But eventually both these groups need to come together on a common model to verify the complete hardware and the embedded software together. Unfortunately, for most teams that first complete model is the actual silicon.
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