|
This document illustrates the Esterel language and coding style, using the example of a 4-bit parallel-to-serial converter. We implement the converter in Esterel and in the standard Hardware Description Languages (HDL), VHDL and Verilog, and we explain the differences. We also compare the simulation of Esterel with the simulation of standard HDLs. Last, we briefly present how verification and synthesis activities are performed in Esterel.
|
||||||
|
||||||
|
||||||
