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Featured Paper by Chandrasekar Rajanayagam Our previous ASIC verification environment lacked the flexibility to easily accommodate changes to our core architecture. Replacing design modules, adding new functionality and reintegrating them consumed valuable time and resources in our project cycle. We decided to take a different approach for our next ASIC, and implement the Synopsys Reference Verification Methodology (RVM) and Vera. Our goal was to minimize the verification schedule, discover bugs early in the design cycle and ensure a successful tape-out. This paper describes how we used RVM to build a functional verification environment for a DVB-S2 receiver ASIC to achieve a first time successful tape-out. Details of our approach on constraint driven random inputs, functional verification and coverage information is discussed. The paper also mentions how using RVM saved us time on integration and more importantly portability and reusability.
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