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RFICs are becoming more complex, packing several functions and supporting multiple frequency bands and wireless standards. Modeling inductance in its intended (e.g. spiral) and parasitic forms is crucial for successful design. This is uniquely handled by Helic’s VeloceRF™ tool, which rapidly models inductance across the chip and produces RLCK netlists. Netlist size and appropriateness for simulation is of concern, particularly for large-scale designs dominated by interconnect parasitics and mutual inductances.
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