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Title : [EN] "How do you qualify netlist reduction and circuit extraction?"
Company : EDXACT SA
Date : 26-May-2011
Downloads : 1

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The significant burden of parasitics on the performance of post-layout verification forces design engineers to use additional techniques in order to match the requirements of next generation designs. A real gap appears between layout extraction and circuit simulation when adding layout parasitics into the flow. A review of the existing techniques as well as a merciless way to doubtlessly validate netlist reduction and circuit extraction are presented in this paper.
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