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A H.264 decoder system is implemented using iNTUITION in which ARM11, LCD, FPGA and various memories are used. The H.264 decoder core is implemented as an AMBA AHB slave IP so that it can be easily integrated with the AMBA-based SoC. The decoder is designed to cooperate with special SDRAM controller utilizing SDRAM page mode to maximize the memory bandwidth at the lowest memory operation speed for low-power application.
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