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A Smart Synchronizer - Pragmatic way to cross asynchronous clock domains. DVCon 20114422-Mar-2011
Achieving First-Time Success with a UPF-based Low Power Verification Flow DVCon 20111422-Mar-2011
Addressing the verification challenge of SERDES-based FPGAs: The performance/accuracy/efficiency trade-off DVCon 2011922-Mar-2011
An Automatic Visual System Performance Stress Test for TLM Designs DVCon 20111022-Mar-2011
An experience to finish code refinement earlier at behavioral level DVCon 2011622-Mar-2011
Automated approach to Register Design and Verification of complex SOC DVCon 20113522-Mar-2011
CompMon: Ensuring Rigorous Protocol Specification and IP Compliance DVCon 2011722-Mar-2011
Exhaustive Equivalence Checking on AMD’s Next-generation Microprocessor Core DVCon 2011722-Mar-2011
From the Magician’s Hat: Developing a Multi-Methodology PCIe Gen2 VIP DVCon 20111122-Mar-2011
Functional coverage-driven verification with SystemC on multiple level of abstraction DVCon 20111822-Mar-2011
Getting Rid of False Errors when Verifying LSI Designs Including Non-Determinism DVCon 2011922-Mar-2011
Low Power Static Verification- Beyond Linting and Corruption Semantics DVCon 20111122-Mar-2011
Off To The Races With Your Accelerated SystemVerilog Testbench DVCon 20111122-Mar-2011
Optimizing Area and Power Using Formal Methods DVCon 20111622-Mar-2011
Panning for Gold in RTL Using Transactions DVCon 2011822-Mar-2011
Pay Me Now or Pay Me Later DVCon 20111022-Mar-2011
Simple & Rapid Design Verification using SystemVerilog Testbench on Intel’s Next-Generation Microprocessor DVCon 20111422-Mar-2011
Stepwise Refinement and Reuse: The Key to ESL DVCon 2011822-Mar-2011
Transaction-Based Acceleration—Strong Ammunition In Any Verification Arsenal DVCon 2011922-Mar-2011
Traversing the Interconnect: Automating Configurable Verification Environment Development DVCon 2011922-Mar-2011
Verification Patterns in the Multicore SoC Domain DVCon 20111722-Mar-2011
Advanced Testbench Configuration with Resources DVCon 20111421-Mar-2011
An Innovative Methodology for Verifying Mixed-Signal Components DVCon 20111221-Mar-2011
Application of SystemC/SystemC-AMS in 3G Virtual Prototyping DVCon 20112421-Mar-2011
Assertion Based Self-checking of Analog Circuits for Circuit Verification and Model Validation in SPICE and Co-simulation Environments DVCon 2011921-Mar-2011
Comparison of TLM2-Quantum Keeping and TLM+-Resource Modeling with regard to Timing in Virtual Prototypes DVCon 2011621-Mar-2011
GoldMine: Automatic Assertion Generation and Coverage Closure in Design Validation DVCon 20111321-Mar-2011
High-Level Synthesis Walks the Talk: Synthesizing a Complete Graphics Processing Application DVCon 2011721-Mar-2011
Linking Multiple Verification Flows Using Automatically Generated Assertions DVCon 2011921-Mar-2011
Low-Power Verification Success Depends on Positive Pessimism DVCon 2011521-Mar-2011
Metric Driven Verification of Mixed-Signal Designs DVCon 2011821-Mar-2011
Mixed Signal Assertion-Based Verification DVCon 20111121-Mar-2011
Parallel Computing for Functional Verification and Compute Farms: The Holy Matrimony DVCon 20111321-Mar-2011
Plan & Metric Driven Mixed-Signal Verification for Medical Devices DVCon 2011721-Mar-2011
Plugging the Holes: SystemC and VHDL Functional Coverage Methodology DVCon 20111121-Mar-2011
Power-aware IP and Mixed-Signal Verification DVCon 2011621-Mar-2011
TLM-2.0 in SystemVerilog DVCon 20111721-Mar-2011
UVM TRANSACTION RECORDING ENHANCEMENTS DVCon 20111121-Mar-2011
A Practical Look @ SystemVerilog Coverage – Tips, Tricks, and Gotchas DVCon 20111719-Mar-2011
Command Line Debug Using UVM Sequences DVCon 2011819-Mar-2011
Consistent SystemC and VHDL Code Generation from State Charts for Virtual Prototyping and RTL Synthesis DVCon 2011719-Mar-2011
Easier UVM for Functional Verification by Mainstream Users DVCon 20112119-Mar-2011
OVM & UVM Techniques for Terminating Tests DVCon 20111719-Mar-2011
So There’s My Bug! Debugging Universal Verification Methodology (UVM) Environments DVCon 20111419-Mar-2011
SystemVerilog FrameWorksTM Scoreboard: An Open Source Implementation Using UVM DVCon 20111219-Mar-2011
Towards Provable Protocol Conformance of Serial Automotive Communication IP DVCon 2011419-Mar-2011
Total 46 links listed, not including links in sub-categories.



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