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Title
Company
Views
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A Guide to Building Faster Simulation Farms: It’s Not Just the CPU Clock Speed
Popular
Cadence Design Systems, Inc.
346
16-Jun-2007
Practical Multi-Gigahertz Clocks for ASIC and COT Designs
OEA International, Inc.
258
09-Mar-2009
Designing a Safe Multi-Clock Chip with Clock Intent Verification
Real Intent, Inc.
334
05-Mar-2004
Dynamic Power-Down Of Peripherals - Issues And Remedies (Texas Instruments India (P) LTD.)
Texas Instruments India (P) Ltd.
200
05-Mar-2004
IEEE 1076.6-200X: VHDL Synthesis Coding Styles for the Future
SynthWorks Design Inc.
281
05-Mar-2004
Multilayered IP For System Level Verification
Paradigm Works
220
05-Mar-2004
Total 6 links listed, not including links in sub-categories.
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Corporate Newsletters
AWR E-News Jan. 2011: Thermal Analysis White Paper and SDR Application Note
KiloPass MemoryPill, Issue #1 January 2012
News from Apache Design - January 2012
Cadence News Jan. 2012: Save on CDNLive! - New Advanced Verification Book - 2012 Forecast
Aldec Design and Verification Newsletter Q1, 2012
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DVCon 2012 Technical Program and Registration, Feb. 27 - Mar. 1
Common Platform Technology Forum, March 14: A Decade of Invention… A World of Solutions
Sensors - Technology, Design & Application - March 21 Santa Clara CA
Call for Papers - ASQED 2012, Malaysia due April 4
ICCAD 2012: Preliminary Call for Papers due April 16
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Russ Henke
EDA Weekly
Silicon Valley: EDA Magnet!
Since this writer began the current series of EDA WEEKLY articles back in November 2009, the exploits of …
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EDA Careers Corner & More
A BILLION DOLLAR AQUSITION YEAR...WOW... The Synopsys Magma Merger, what it really means to Careers...My take on Career Prospects for 2012
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Dr. Russ Henke
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