| Title |  |  |
|
| Company | | |
| Views |
| Added | | |
|
| Randomization and Functional Coverage in VHDL New | Aldec | 13 | 12-Jan-2012 |
| Multicycle path analysis and verification in static timing analysis Popular | ASICServe | 173 | 16-Aug-2011 |
| Expect faster adoption of IDEs in hardware design and verification | AMIQ | 24 | 28-Jun-2011 |
| A Comparison of Embedded Non-Volatile Memory Technologies and Their Applications | Kilopass | 35 | 17-Jun-2011 |
| Methods for Configurable Hardware Design | Kilopass | 33 | 17-Jun-2011 |
| Profitable SoC Design: Using Logic NVM to Reduce SoC Costs | Kilopass | 13 | 17-Jun-2011 |
| Three Application Segments Require On-Chip OTP | Kilopass | 15 | 17-Jun-2011 |
| Studying Clock Recovery Performance using IBIS-AMI Models | SiSoft | 55 | 24-Mar-2011 |
| Gates-on-the-Fly fixes Logic Equivalence Check Failures | SynaptiCAD, Inc. | 49 | 17-Sep-2010 |
| Digital Place and Route in a Custom Design Environment | SpringSoft, Inc. | 41 | 16-Aug-2010 |
| PCell Caching in OpenAccess | SpringSoft, Inc. | 46 | 26-Jul-2010 |
| Challenges and Requirements for Power-Aware Degug | SpringSoft, Inc. | 17 | 11-Mar-2010 |
| Introducing Functional Qualification | SpringSoft, Inc. | 17 | 11-Mar-2010 |
| Considerations for Bulk CMOS to FD-SOI Design Porting New | SOI Industry Consortium | 1 | 06-Dec-2011 |
| Advanced On-chip-variation Timing Analysis for Nanometer Designs Popular | Incentia | 518 | 14-Jun-2011 |
| 60nm and 90nm Interconnect Modeling Chalenges Popular | OEA International, Inc. | 353 | 13-Apr-2011 |
| Transaction-Level Modelling and Debug of SoCs Popular | SpringSoft, Inc. | 254 | 03-Jan-2009 |
| Tutorial: The Changing World of Signal Integrity - Challenges and Solutions Popular | AWR Corporation | 400 | 06-Feb-2008 |
| Coding Techniques for Bus Functional Models In Verilog, VHDL, and C++ Popular | SynaptiCAD, Inc. | 204 | 14-Dec-2007 |
| Timing (Analysis) is Everything: A How-To Guide for Timing Analysis Popular | SynaptiCAD, Inc. | 228 | 14-Dec-2007 |
| EDA Survey Results Popular | Synopsys Inc. | 535 | 29-Jun-2006 |
| Using Signal Integrity Analysis to Achieve EMC Popular | SIGRITY, Inc. | 157 | 13-Apr-2006 |
| Hierarchical Static Timing Analysis at Bull with HiTas Popular | Avertec Inc. | 138 | 10-Jan-2006 |
| 2002 ISD Magazine Article: Hidden Complexities of PLLs Are Revealed Popular | True Circuits, Inc. | 461 | 15-Jul-2004 |
| Going Beyond 32-bit - EDA Linux Computing Popular | Hewlett Packard | 571 | 01-Jun-2004 |
| Debugging SCE-MI Co-Emulation in Riviera-PRO™ Simulation Environment | Aldec | 0 | 02-Dec-2011 |
| //yx channel_transform Channel to Channel Assignment Guidelines | Y Explorations, Inc. | 0 | 25-Sep-2011 |
| Collaborative design of the FIR Filter Based Hardware and Software | Y Explorations, Inc. | 0 | 25-Sep-2011 |
| System-Level Design Tools and RTOS for Multiprocessor SoCs | Y Explorations, Inc. | 1 | 25-Sep-2011 |
| HIGH SPEED CMOS ANALOG-TO-DIGITAL CONVERTER CIRCUIT FOR RADIO FREQUENCY SIGNAL | Micro Magic, Inc. | 1 | 13-Sep-2011 |
| Trenz Electronic GigaBee XC6SLX series user manual | Trenz Electronic GmbH | 0 | 11-Sep-2011 |
| VN-Spec / vManager Interoperability Brief | TransEDA | 0 | 11-Sep-2011 |
| BSIM3v3.1 Model Parameter Extraction & Optimization | The MOSIS Service | 0 | 09-Sep-2011 |
| Zeit ist Geld – Echtzeit ist viel Geld Timingoptimierungen bei der Aktivlenkung von BMW | Symtavision GmbH | 0 | 03-Sep-2011 |
| Enhanced interconnect medium simplifies test & verification | Ironwood Electronics | 0 | 30-Aug-2011 |
| IC Socket Footprint – Why is it important? | Ironwood Electronics | 0 | 30-Aug-2011 |
| Package Converter Compliments Chip Obsolescence | Ironwood Electronics | 0 | 30-Aug-2011 |
| Role of Sockets in IC Product Life Cycle | Ironwood Electronics | 0 | 30-Aug-2011 |
| AWR® iFilter™ Application Note | AWR Corporation | 1 | 27-Aug-2011 |
| Adapting AMI to Support Back-Channel Communications | SIGRITY, Inc. | 3 | 24-Aug-2011 |
| Analyzing Chips in a System Context | SIGRITY, Inc. | 1 | 24-Aug-2011 |
| Antenna Design | IMST GmbH | 2 | 21-Aug-2011 |
| IMST Imagefolder | IMST GmbH | 0 | 21-Aug-2011 |
| Global Design Data Management Report 2010 | IC Manage, Inc. | 1 | 19-Aug-2011 |
| Global Design Management Report 2011 | IC Manage, Inc. | 0 | 19-Aug-2011 |
| Designing a CE-ATA Verification Environment for SoC Applications | Globetech Solutions | 0 | 26-Jul-2011 |
| New Methodology on Electro-Thermal Characterization and Modeling of Large Power Drivers Using Lateral PNP BJTs | Gradient Design Automation Inc. | 0 | 26-Jul-2011 |
| Practical chip-centric electro-thermal simulations | Gradient Design Automation Inc. | 0 | 26-Jul-2011 |
| STIL Verifier: Post-Silicon Functional Test Automation within Cadence Incisive | Globetech Solutions | 0 | 26-Jul-2011 |
| Thermal Properties and Reliability of GaN Microelectronics | Gradient Design Automation Inc. | 1 | 26-Jul-2011 |
| The two "wildly different" reasons we bought Arithmatica | Forte Design Systems | 1 | 15-Jul-2011 |
| Eliminating Embedded Non-Volatile Memory IP Risks in SOCs | Kilopass | 1 | 17-Jun-2011 |
| Integrating High Density Antifuse OTP NVM for Code Storage | Kilopass | 2 | 17-Jun-2011 |
| Kilopass Brings Gusto to Memory | Kilopass | 0 | 17-Jun-2011 |
| Secure, Low-cost On-Chip Code Storage for Embedded Signal-Processing Systems | Kilopass | 0 | 17-Jun-2011 |
| Interconnect Delay Compensation in Timing Analysis for Designs Containing Multiple Voltage Domains | Incentia | 48 | 03-Jun-2011 |
| Advanced On-chip-variation Timing Analysis for Nanometer Designs, Part II | Incentia | 76 | 17-May-2011 |
| Fast controller development | dSPACE GmbH | 1 | 14-May-2011 |
| Silicon Realization—A New Approach to Faster, Better, and More Profitable Silicon | Cadence Design Systems, Inc. | 4 | 29-Apr-2011 |
| dw-2000TM HLVS | Design Workshop, Inc. | 1 | 24-Apr-2011 |
| Photonics Element Library | Design Workshop, Inc. | 0 | 24-Apr-2011 |
| Common Pitfalls in Ethernet Designs at Ethernet Alliance 2011 | MIPI Alliance 2011 | 1 | 01-Apr-2011 |
| Common Pitfalls in MIPI HSI Designs at MIPI Alliance 2011 | MIPI Alliance 2011 | 5 | 01-Apr-2011 |
| Complete NAND Flash Solution: Logic, PHY and File System Software | Arasan Chip Systems | 3 | 24-Mar-2011 |
| Facilitating Unreachable Code Diagnosis and Debugging | Avery Design Systems, Inc | 3 | 12-Mar-2011 |
| Finding Reset Nondeterminism in RTL Designs – Scalable X-Analysis Methodology and Case Study | Avery Design Systems, Inc | 3 | 12-Mar-2011 |
| Interoperable IP Delivery | Aldec | 8 | 11-Mar-2011 |
| “iWave announced its i.MX53 SOM on the same day Freescale announced the availability of its i.MX53 SoC” | iWave Systems Technologies Pvt.Ltd | 0 | 05-Mar-2011 |
| Creating Virtual Platform using The OCP-IP Modeling kit | CircuitSutra Technologies Pvt Ltd. | 0 | 23-Feb-2011 |
| Accelerating Innovation in Electronic Product Development | Dassault Systèmes | 10 | 27-Oct-2010 |
| Verilog Test Suites | Verific Design Automation Inc. | 107 | 06-Oct-2010 |
| The economies of outsourcing | Verific Design Automation Inc. | 30 | 02-Oct-2010 |
| DO-254 In-Hardware Verification | Aldec | 12 | 16-Sep-2010 |
| Dynamic Design Analysis - Data Mining For Verification Closure | AXIOM Design Automation | 20 | 02-Sep-2010 |
| What's New in VSS v2009 | Applied Wave Research, Inc. (AWR) | 0 | 19-Aug-2010 |
| The Inefficiency of C++, Fact or Fiction? | IAR Systems | 0 | 27-Jul-2010 |
| Formal Analysis: A Valuable Tool for Post-Silicon Debug | Jasper Design Automation | 6 | 16-Jul-2010 |
| Survey of Chip Designers on the Value of Formal Verification Across the Spectrum of Applications | Jasper Design Automation | 10 | 16-Jul-2010 |
| Toward Harnessing the True Potential of IP Reuse | Jasper Design Automation | 7 | 16-Jul-2010 |
| Applying Formal Methods to a PCI-Express Transmit Retry Buffer | Jasper Design Automation | 15 | 15-Jul-2010 |
| Formal Verification Deployment Reveals Return On Investment | Jasper Design Automation | 11 | 15-Jul-2010 |
| A Guide to Power-Aware Memory Repair | Mentor Graphics | 77 | 13-Jul-2010 |
| Two Major Shifts Impacting Software Development Productivity | Spatial | 1 | 15-Jun-2010 |
| GiDEL COTs Solutions | GiDEL | 3 | 07-Jun-2010 |
| Formal Verification for Challenging Low-Power Designs | Jasper Design Automation | 26 | 27-May-2010 |
| Cadence EDA360 Vision Paper | Cadence Design Systems, Inc. | 31 | 30-Apr-2010 |
| ZeBu™: A Unified Verification Approach for Hardware Designers and Embedded Software Developers | Eve, Inc. | 12 | 22-Apr-2010 |
| Invarian Addresses Sign-Off Predictability Issues With Concurrent Analysis For Power, Voltage, Temperature, And Timing | Invarian | 8 | 16-Apr-2010 |
| Advanced Scgematic-Driven Layout Automation | SpringSoft, Inc. | 18 | 11-Mar-2010 |
| Predicting BER with IBIS-AMI: experiences correlating SerDes simulations and measurement | SiSoft | 48 | 05-Mar-2010 |
| Automated DRC Waiver Management | Mentor Graphics | 126 | 04-Feb-2010 |
| Combining Low Pin Count Test with Scan Compression Dramatically Reduces Test Interface and Cost | Mentor Graphics | 99 | 04-Feb-2010 |
| ENABLING ASSERTION BASED VERIFICATION | Zocalo Tech | 18 | 12-Jan-2010 |
| Accelerating CRCs on eSi-RISC with user-defined instructions | EnSilica Ltd | 1 | 10-Jan-2010 |
| System Verilog + OVM: Mitigating Verification Challenges & Maximizing Reusability | AppliedMicro (AMCC) | 19 | 23-Dec-2009 |
| Deliver smarter products with requirements engineering. | IBM | 37 | 21-Dec-2009 |
| Theory and Best Practice of RSA Compute Offload Processor Design | Crack Semiconductor | 3 | 19-Dec-2009 |
| Practical Applications of Data Abstraction Techniques for Embedded Systems Debug | SpringSoft, Inc. | 21 | 13-Dec-2009 |
| Visibility Enhancement for Silicon Debug | SpringSoft, Inc. | 10 | 13-Dec-2009 |
| Transaction-based Debug of PCI Express Embedded SoC Platforms | SpringSoft, Inc. | 37 | 12-Dec-2009 |
| LTE EPC: Drivers and Bene fits o f Pre-Inte grate d F rame works VERSION | RadiSys | 0 | 02-Dec-2009 |
| The Enea System Manager | RadiSys | 0 | 02-Dec-2009 |
| Design Philosophy and Methodology | Shax Engineering and Systems | 13 | 28-Nov-2009 |
| A Low-Cost Task Specific Solution for IO Pad-Ring and Package Net List Construction | SIGRITY, Inc. | 3 | 27-Nov-2009 |
| Trends and Requirements for System-Level Design of Signal and Power Delivery | SIGRITY, Inc. | 2 | 27-Nov-2009 |
| Graphical Test Bench Generation | SynaptiCAD, Inc. | 2 | 18-Nov-2009 |
| 10 Tips for Successful SOC Design | Tensilica | 19 | 14-Nov-2009 |
| Cut DSP Development Time – Get High Performance From C, No Assembly Required | Tensilica | 2 | 14-Nov-2009 |
| Address System-on-Chip Development Challenges with Enterprise Verification Management | IBM | 172 | 13-Nov-2009 |
| High-Volume nano FPGAs | Actel Corporation | 1 | 03-Nov-2009 |
| Automated Assembly and IP Integration Techniques for SoCs | Atrenta | 17 | 29-Oct-2009 |
| Verification of Multi-Clock Designs | Atrenta | 61 | 29-Oct-2009 |
| The formal verification market is still untapped | Olivier Coudert | 6 | 22-Oct-2009 |
| Employing Risk Management Techniques to Mitigate Technological and Market Pitfalls -- The Challenges and Realities of High-Performance and Low Power SoC Designs | Virage Logic | 16 | 19-Oct-2009 |
| Automated low-power design flow is up for grabs | Olivier Coudert | 26 | 07-Oct-2009 |
| Across the Great Divide… | Jasper Design Automation | 8 | 07-Oct-2009 |
| Advanced Schematic-Driven Layout Automation | SpringSoft, Inc. | 32 | 07-Oct-2009 |
| Verification Intellectual Property (VIP) Best Practices Interoperability Guide. | Acellera | 16 | 05-Oct-2009 |
| Assertion-Based Hardware Debugging - presented at DVCon | SpringSoft, Inc. | 101 | 03-Oct-2009 |
| Design and Debug with Advanced Languages: Challenges and Opportunities for SystemVerilog- presented at DVCon | SpringSoft, Inc. | 113 | 03-Oct-2009 |
| Solving Your Top Four Engineering Challenges | Open Text | 32 | 02-Oct-2009 |
| 3D Modeling and Analysis in EDA Applications | Spatial | 38 | 22-Sep-2009 |
| EMPOWERING DESIGN FOR QUALITY OF SILICON | Cadence Design Systems, Inc. | 101 | 13-Sep-2009 |
| High-Performance, High-Precision Memory Characterization | Altos | 5 | 28-Jul-2009 |
| Small but Deadly : The Life Cycle of an I/O Bug | Duolog Technologies | 7 | 10-Jul-2009 |
| Enabling System-level Electrical Co-design for Mixed-Signal Systems | PhysWare | 37 | 09-Jul-2009 |
| Challenges and Requirements for Power-Aware Debug | SpringSoft, Inc. | 13 | 02-Jul-2009 |
| A Register Transfer Level Approach to Memory Built-in Self Test and Repair Insertion | Atrenta | 19 | 16-Jun-2009 |
| A Register Transfer Level Approach to Memory Built-in Self Test and Repair Insertion | Atrenta | 15 | 16-Jun-2009 |
| Automated Assembly and IP Integration Techniques for SoCs | Atrenta | 5 | 16-Jun-2009 |
| CHALLENGES AND REQUIREMENTS FOR POWER-AWARE DEBUG | SpringSoft, Inc. | 19 | 16-Jun-2009 |
| Combining Structural and Functional Verification Techniques to Improve Effective CDC Verification | Atrenta | 13 | 16-Jun-2009 |
| Constraints Management: Approach and Techniques for Preserving the Intent of Timing Constraints throughout the Design Flow | Atrenta | 21 | 16-Jun-2009 |
| Designing for Test at RTL | Atrenta | 17 | 16-Jun-2009 |
| Estimating Fault Coverage from RTL without Fault Simulation | Atrenta | 15 | 16-Jun-2009 |
| Facilitating At-speed Test at RTL | Atrenta | 5 | 16-Jun-2009 |
| GuideWare™ | Atrenta | 13 | 16-Jun-2009 |
| SpyGlass Application in an FPGA to ASIC Conversion | Atrenta | 10 | 16-Jun-2009 |
| Physware's Parallelization Methodology | PhysWare | 10 | 27-May-2009 |
| The Interpretation of Non-Zero Mutual Resistances in PhysAPEX | PhysWare | 3 | 27-May-2009 |
| Data Security in Logic Non-Volatile Memory Technologies | Virage Logic | 10 | 20-May-2009 |
| Logic NVM Versus Embedded Flash Technology and Economic Tradeoffs | Virage Logic | 37 | 20-May-2009 |
| How to Improve Multisite Design Team Productivity in Uncertain Times | Cliosoft, Inc. | 16 | 23-Apr-2009 |
| 3D EM Simulation in the Design Flow of High-Speed Multi-Pin Connectors | CST-Computer Simulation Technology | 20 | 23-Mar-2009 |
Best Paper Award at DesignCon -
A Simple Via Experiment | SiSoft (Signal Integrity Software, Inc.) | 95 | 25-Feb-2009 |
| Novas Verdi Helps Navigate Unfamiliar Territory to Achieve IC Design Harmony: From 1st Hire to 1st Tapeout in 8 Months | SpringSoft, Inc. | 58 | 07-Feb-2009 |
| SigmaTel Relies on Verdi Debug System As Critical Element in Verification Strategy | SpringSoft, Inc. | 19 | 07-Feb-2009 |
| Design of ST planar integrated inductors based on INFINISCALE flow | InfiniScale® | 4 | 21-Jan-2009 |
| Process Optimization | Ingenuus Software Inc. | 8 | 21-Jan-2009 |
| OSCI TLM2.0 Standard Compliance –Why Bother? | Jeda Technologies, Inc. | 6 | 17-Jan-2009 |
| Debug Automation Backgrounder | SpringSoft, Inc. | 13 | 07-Jan-2009 |
| Visibility Enhancement for Simulation Methodology Backgrounder | SpringSoft, Inc. | 6 | 07-Jan-2009 |
| Visibility Enhancement Technology for Simulation | SpringSoft, Inc. | 15 | 07-Jan-2009 |
| SystemVerilog Assertion Backgrounder | SpringSoft, Inc. | 82 | 04-Jan-2009 |
| A study of the thermal characterization of a high – performance flip chip package | Endicott Interconnect Technologies | 6 | 02-Jan-2009 |
| An Experimental and Computational Study of the Current Carrying Capacity of High Performance PWB Interconnections | Endicott Interconnect Technologies | 2 | 02-Jan-2009 |
| Laser Micromachining of Barium Titanate (BaTiO3)-Epoxy Nanocomposite-Based Flexible/Rollable Capacitors: New Approach for Making Library of Capacitors | Endicott Interconnect Technologies | 5 | 02-Jan-2009 |
| Resin Coated Copper Capacitive (RC3) Nanocomposites for Multilayer Embedded Capacitors | Endicott Interconnect Technologies | 1 | 02-Jan-2009 |
| Addressing 3D Packaging Challenges | SIGRITY, Inc. | 6 | 17-Dec-2008 |
| Enabling Predictable Low Power Design and Implementation | Cadence Design Systems, Inc. | 10 | 17-Dec-2008 |
| Efficient Noise Analysis for Complex Non-Periodic Analog/RF Blocks | Berkeley Design Automation, Inc. | 28 | 12-Dec-2008 |
| A Practical Approach to Preventing Simultaneous Switching Noise and Ground Bounce Problems in IO Rings | OEA International, Inc. | 18 | 07-Dec-2008 |
| A dynamic hardware video processing platform | Andraka Consulting Group Inc | 6 | 04-Dec-2008 |
| An Onboard Processor and Adaptive Scanning Controller for the Second-Generation Precipitation Radar | Andraka Consulting Group Inc | 2 | 04-Dec-2008 |
| Building a High Performance Bit Serial Processor in an FPGA | Andraka Consulting Group Inc | 12 | 04-Dec-2008 |
| FIR Filter Fits in an FPGA using a Bit Serial Approach | Andraka Consulting Group Inc | 9 | 04-Dec-2008 |
| High Performance Digital Down-Converters for FPGAs | Andraka Consulting Group Inc | 9 | 04-Dec-2008 |
| Unveiling the next generation in substrate Technology | Amkor Technology, Inc. | 12 | 03-Dec-2008 |
| Analog & Mixed Signal IC Debug: A high precision ADC application | Dolphin Integration | 8 | 01-Dec-2008 |
| A Practical Guide to Low-Power Design -- User Experience with CPF | Power Forward Initiative | 34 | 26-Nov-2008 |
| Parallelization using Polyhedral Analysis | ACE Associated Compiler Experts bv | 4 | 25-Nov-2008 |
| The Many Flavors of Low-Power, Low-Cost FPGAs | Actel Corporation | 3 | 25-Nov-2008 |
| An Efficient, Interactive Optimization Solution for Analog and RF | AWR Corporation | 28 | 10-Nov-2008 |
| AWR VSS 2006 Offers A Comprehensive, Specification-Compliant Solution for WiMAX Systems Design | AWR Corporation | 29 | 10-Nov-2008 |
| SPIRAL INDUCTOR MODELING ON RFICs | AWR Corporation | 61 | 10-Nov-2008 |
| SystemVerilog Testbench Debug And Analysis | Cypress Semiconductor | 81 | 06-Oct-2008 |
| Mobileye Chooses Virage Logic for EyeQ -Game-like interfaces | Virage Logic | 10 | 27-Sep-2008 |
| Crosstalk Analysis of a System Based on XAUI HMZd Evaluation Backplane Data | SiSoft (Signal Integrity Software, Inc.) | 41 | 24-Sep-2008 |
| Design-for-Variability | Teklatech | 36 | 26-Aug-2008 |
| Trace Recording and Performance Analysis XC/XC2000 family, based on TantinoXC | Hitex Development Tools | 2 | 18-Aug-2008 |
| The Voice of the Customer - Process Integration and Traceability through Requirements Management | Dassault Systèmes | 5 | 31-Jul-2008 |
| Signal Integrity and Timing Analysis Simulation Reuse | Signal Integrity Software, Inc. (SiSoft) | 334 | 28-Jul-2008 |
| A Power Integrity Wall Folloes the Power Wall! | Anasim® Corp. | 6 | 24-Jul-2008 |
| Straightforward IP Integration with IP-XACT RTL-TLM Switching | Evatronix S.A. | 8 | 15-Jul-2008 |
| Record-Breaking - 1 day with PROC Board does more then 256 PCs * 14 days. | GIDEL | 23 | 01-May-2008 |
| Features and Implementation of High-Performance 667Mbs and 800Mbs DDRII Memory Systems | SiSoft (Signal Integrity Software, Inc.) | 36 | 10-Apr-2008 |
| How to Back Annotate in ORCAD after re-sequencing is done in Allegro Layout. | Baykal Technology, Inc. | 16 | 04-Apr-2008 |
| How to transfer Schematics Properties from ORCAD to Allegro Layout Software | Baykal Technology, Inc. | 32 | 04-Apr-2008 |
| Demonstration of SerDes Modeling using the Algorithmic Model Interface (AMI) Standard | SiSoft (Signal Integrity Software, Inc.) | 56 | 24-Mar-2008 |
| System Level Timing Closure using HSPICE | SiSoft (Signal Integrity Software, Inc.) | 47 | 24-Mar-2008 |
| Development Of A Development Of A Real-Time Simulation System | Applied Dynamics International | 6 | 19-Mar-2008 |
| Distributed HIL Simulation | Applied Dynamics International | 6 | 19-Mar-2008 |
| Predictor Methods in Real-time Simulation | Applied Dynamics International | 5 | 19-Mar-2008 |
| Test Automation with the ADvantage Simulation Framework | Applied Dynamics International | 3 | 19-Mar-2008 |
| A Low Complexity Method for Detecting Configuration Upset in SRAM Based FPGAs | Andraka Consulting Group Inc | 5 | 18-Mar-2008 |
| AN ULTRA-LOW POWER SUBBAND-BASED ELECTRONIC STETHOSCOPE | AMI Semiconductor | 16 | 16-Mar-2008 |
| LOW-POWER IMPLEMENTATION OF AN HMM-BASED SOUND ENVIRONMENT CLASSIFICATION ALGORITHM FOR HEARING AID APPLICATION | AMI Semiconductor | 8 | 16-Mar-2008 |
| Real-Time Cardiac Arrhythmia Detection Using WOLA Filterbank Analysis of EGM Signals | AMI Semiconductor | 2 | 16-Mar-2008 |
| Ultra-Low-Power Application Development with RCore C and Assembler | AMI Semiconductor | 7 | 16-Mar-2008 |
| Practical Multi-Gigahertz Clocks for ASIC and COT Designs | Multigig, Inc. | 5 | 14-Mar-2008 |
| Power Integrity and Energy aware Floor Planning | Anasim® Corp. | 17 | 20-Feb-2008 |
| Drowsy Caches: Simple Techniques for Reducing Leakage Power | ARM Inc | 13 | 08-Feb-2008 |
| Thread-level Parallelism and Interactive Performance of Desktop Applications | ARM Inc | 11 | 08-Feb-2008 |
| A Conservative Extension of Synchronous Dataflow with State Machines | Esterel Technologies | 1 | 17-Jan-2008 |
| Certified Development Tools Implementation in Objective Caml | Esterel Technologies | 0 | 17-Jan-2008 |
| Open Software Development Platforms for Safety Critical Applications in the Rail/Transportation Domain | Esterel Technologies | 1 | 17-Jan-2008 |
| Semantics of S.S.M (Safe State Machine) | Esterel Technologies | 2 | 17-Jan-2008 |
| The Synchronous Dataflow Programming Language LUSTRE | Esterel Technologies | 0 | 17-Jan-2008 |
| Type-Based Initialization Analysis Of A Synchronous Data-Flow Language | Esterel Technologies | 0 | 17-Jan-2008 |
| A compact Microstrip Stepped-Impedance Resonator and Filter (Microwave Journal) | Ansoft LLC | 23 | 16-Jan-2008 |
| A Miniaturized GaAs MMIC Bandpass Filter for the 5 GHz Band (Microwave Journal) | Ansoft LLC | 31 | 16-Jan-2008 |
| Protocol Dictates Requirements For RFID ICs (Microwaves & RF) | Ansoft LLC | 18 | 16-Jan-2008 |
| View From The Top (Microwave Product Digest) | Ansoft LLC | 13 | 16-Jan-2008 |
| Interfacing VHDL and Verilog Designs to C++ Models | SynaptiCAD, Inc. | 64 | 14-Dec-2007 |
| Adding Video to SOCs: The Diamond 388VDO Video Engine | Tensilica | 14 | 08-Oct-2007 |
| Automated Configurable Processor Design Flow (PDF) | Tensilica | 37 | 08-Oct-2007 |
| Building a Multi-Issue DSP with Configurable Processor Technology | Tensilica | 16 | 08-Oct-2007 |
| Configurable Processors: What, Why, How? | Tensilica | 59 | 08-Oct-2007 |
| Developing a High-Performance, Programmable MPEG-4 Decoder by Adding a Programmable SIMD Engine to a Configurable, Extensible Microprocessor | Tensilica | 20 | 08-Oct-2007 |
| Diamond Standard Series Architecture White Paper (PDF) | Tensilica | 14 | 08-Oct-2007 |
| Flexible VDSL2 Datapath IP for SOC Designs Provides Ready Access to the VDSL2 chip market | Tensilica | 8 | 08-Oct-2007 |
| Low-Power, Low-Overhead, High-Fidelity Digital Sound for SOCs: Tensilica’s HiFi 2 Audio Engine | Tensilica | 13 | 08-Oct-2007 |
| Processor Core Power Specs: A Cautionary Tale | Tensilica | 16 | 08-Oct-2007 |
| Tensilica Xtensa LX Processor with Vectra LX By BDTI | Tensilica | 12 | 08-Oct-2007 |
| Why High MHz Does Not Mean High Performance | Tensilica | 30 | 08-Oct-2007 |
| XPRES Compiler: Triple-Threat Solution to Code Performance Challenges | Tensilica | 8 | 08-Oct-2007 |
| XPRES White Paper: Rapid SOC Development using Automatically Generated Processors | Tensilica | 12 | 08-Oct-2007 |
| Xtensa Architecture White Paper (PDF) | Tensilica | 16 | 08-Oct-2007 |
| Complex Register Verification Utilizing RVM Based Register Abstraction Layer (RAL) | Cypress Semiconductor | 78 | 30-Sep-2007 |
| Avoiding the Pitfalls of Polymorphism Or How to build an Extendable Verification Environment | IBM | 16 | 27-Sep-2007 |
| 60 GHz Transceiver IC Design Using High-Mobility .15-micron GaAs Process | Ansoft LLC | 15 | 30-Aug-2007 |
| Refference Flow For High-Speed Serial Interconnect Design | Ansoft LLC | 28 | 30-Aug-2007 |
| RFID Radio Circuit Design in CMOS | Ansoft LLC | 47 | 30-Aug-2007 |
| Flash Support for XC166 with XC_Flasher / Usage and Interface of Flash Control DLL (fxc_cntrl.dll) | Hewlett Packard | 7 | 18-Aug-2007 |
| Resolving EMI Problems with Good Power Delivery Strategy | Huawei Technologies | 92 | 16-Aug-2007 |
| Advancement in HPC Improves Engineering and Electronic Cooling Simulations | Appro International | 6 | 06-Aug-2007 |
| Altium Corporate Profile (PDF) | Altium Limited | 21 | 26-Jun-2007 |
| Altium Designer Feature Set Summary | Altium Limited | 14 | 26-Jun-2007 |
| Why Choose Altium Designer | Altium Limited | 37 | 26-Jun-2007 |
| Why Partner with Altium | Altium Limited | 10 | 26-Jun-2007 |
| Leakage Power and PowerTheater | Sequence Design, Inc. | 2 | 14-Jun-2007 |
| Next-Generation Electrical Noise Analysis | Berkeley Design Automation, Inc. | 7 | 04-Jun-2007 |
| Precision Circuit Analysis Products | Berkeley Design Automation, Inc. | 16 | 04-Jun-2007 |
| Precision Circuit Analysis™ Technology | Berkeley Design Automation, Inc. | 14 | 04-Jun-2007 |
| 8051 IP Core | Tata Elxsi | 27 | 03-Jun-2007 |
| LIN eVC | Tata Elxsi | 13 | 03-Jun-2007 |
| Tata Elxsi Bridge (AHB to APB Bridge) | Tata Elxsi | 31 | 03-Jun-2007 |
| Lead-Free Now! | Samtec, Inc. | 5 | 02-Jun-2007 |
| Selecting memory controller for DSP systems | Mirabilis Design Inc. | 4 | 01-Jun-2007 |
| Using virtual system prototyping to evaluate VME platforms | Mirabilis Design Inc. | 8 | 01-Jun-2007 |
| Accelerating Integration with Verastream Host Integrator | Attachmate Corporation. | 7 | 30-May-2007 |
| Attachmate Verastream Host Integrator Architecture and Best Practices | Attachmate Corporation. | 5 | 30-May-2007 |
| From Fluid Dynamics to Business Performance | Appro International | 7 | 24-May-2007 |
| 1-SOURCE™ Virtuall Prototyping for Embedded Systems Design | VaST | 2 | 18-Apr-2007 |
| Software Driven Embedded Systems Design | VaST | 5 | 18-Apr-2007 |
| VaST Systems Technology Corporation - Powering Embedded Design Innovation | VaST | 4 | 18-Apr-2007 |
| Virtualized Software Development - Manifesto | VaST | 2 | 18-Apr-2007 |
| AN200701-01A On the DC resistance of printed circuit board ground plane. | Sysacom R&D plus inc. | 12 | 07-Apr-2007 |
| An Electromagnetic Time-Harmonic Analysis of Shielded Microstrip Circuits | Sonnet Software, Inc. | 8 | 05-Apr-2007 |
| Characteristic Impedance - A New Definition of Characteristic Impedance | Sonnet Software, Inc. | 14 | 05-Apr-2007 |
| De-embedding - A De-Embedding Algorithm for Electromagnetics | Sonnet Software, Inc. | 9 | 05-Apr-2007 |
| Planar Electromagnetic Analysis | Sonnet Software, Inc. | 15 | 05-Apr-2007 |
| Planar Electromagnetic Software - Personal Reflections (Microwave Journal: Mar 2005 Cover) | Sonnet Software, Inc. | 9 | 05-Apr-2007 |
| GDSII to OASIS conversion: Performance and Analysis | SoftJin Technologies Private Limited | 6 | 04-Apr-2007 |
| System Verification for Reconfigurable Processor based Systems using SystemC | SoftJin Technologies Private Limited | 12 | 04-Apr-2007 |
| Implementation Independent Design of a Digital Imaging Algorithm Using Behavioral Synthesis | Forte Design Systems | 3 | 21-Mar-2007 |
| Metrics-based Behavioral Design | Forte Design Systems | 5 | 21-Mar-2007 |
| ISSCC 2006 / SESSION 21 / ADVANCED CLOCKING, LOGIC AND SIGNALING TECHNIQUES / 21.6 | Multigig, Inc. | 10 | 13-Mar-2007 |
| New Generation of EDA Tools Can Significantly Improve Low Power Design | Atrenta | 50 | 06-Mar-2007 |
| Architecting, Designing, Implementing, and Verifying Low-Power Digital Integrated Circuits | Cadence Design Systems, Inc. | 73 | 20-Feb-2007 |
| Bluespec SystemVerilog for IP Delivery and Effective RTL Debug | Bluespec, Inc. | 16 | 14-Feb-2007 |
| Fast Yield-Driven Fracture for Variable Shaped-Beam Mask Writing | Blaze DFM, Inc. | 3 | 14-Feb-2007 |
| Lens Aberration-Aware Timing-Driven Placement | Blaze DFM, Inc. | 4 | 14-Feb-2007 |
| BVCER – Increased Operating Voltage for SiGe HBTs | austriamicrosystems USA, Inc. | 7 | 09-Feb-2007 |
| High Voltage CMOS technologies for robust System-on-Chip design | austriamicrosystems USA, Inc. | 12 | 09-Feb-2007 |
| Understanding Integrated Hall Effect Rotary Encoders | austriamicrosystems USA, Inc. | 11 | 09-Feb-2007 |
| Visibility Enhancement for Full-Chip Simulation | Novas | 13 | 22-Jan-2007 |
| Airborne Direct Georeferencing of Frame Imagery: An Error Budget | SimWright, Inc. | 1 | 05-Dec-2006 |
| Coordinate Design and Information System (CDIS) Technology | SiteComp, Inc. | 0 | 05-Dec-2006 |
| Geospecific 3D Stereo Imagery for Rapid Low Cost GIS Data Collection | SimWright, Inc. | 0 | 05-Dec-2006 |
| Integrating Remotely Sensed Imagery And Information for Transportation | SimWright, Inc. | 0 | 05-Dec-2006 |
| IR Drop in High-Speed IC Packages and PCBs | SIGRITY, Inc. | 50 | 15-Nov-2006 |
| Assertion-Based Verification: Choosing the Right Solution | Atrenta | 54 | 25-Oct-2006 |
| Do your Chips a Favor! Manage your Constraints!! | Atrenta | 72 | 25-Oct-2006 |
| Estimating Fault Coverage from RTL without Fault Simulation | Atrenta | 63 | 25-Oct-2006 |
| Atrenta® Predictive Development: Reducing Risk and Enhancing Innovation in Complex System Development | Atrenta | 8 | 25-Oct-2006 |
| Combining Structural and Functional Verification Techniques to Improve Effective CDC Verification | Atrenta | 31 | 25-Oct-2006 |
| Designing for test at RTL | Atrenta | 66 | 25-Oct-2006 |
| Low Power Design: Implications and Options | Atrenta | 95 | 25-Oct-2006 |
| Managing and Measuring RTL Development Progress | Atrenta | 22 | 25-Oct-2006 |
| Total Quality Management: Manual Systems Aren’t Enough | Atrenta | 14 | 25-Oct-2006 |
| A Practical Approach to Process Corner Models of Interconnect RC Extraction | National Semiconductor Corporation | 54 | 05-Oct-2006 |
| RTL Coding Technique for Better Coverage | Cypress Semiconductors India Private Limited | 51 | 30-Sep-2006 |
| Automatic MilkyWay Technology File Generation | Cypress Semiconductor | 37 | 28-Sep-2006 |
| Critical Paths Verification and Debugging with PrimeTime Advanced Features | National Semiconductor Corporation | 61 | 26-Sep-2006 |
| Accelerating System Performance Using ESL Design Tools and | Celoxica | 24 | 12-Sep-2006 |
| Custom Algorithm to an FPGA System Component | Celoxica | 9 | 12-Sep-2006 |
| Implementing Floating-Point DSP | Celoxica | 27 | 12-Sep-2006 |
| Rapidly Design Custom FPGA Components Without the | Celoxica | 8 | 12-Sep-2006 |
| The economies of outsourcing | Verific Design Automation Inc. | 36 | 31-Aug-2006 |
| EDA story so far... | SoftJin Technologies Private Limited | 59 | 21-Aug-2006 |
| Mixed-Signal Design and Verification, Static or Dynamic | Cypress Semiconductor | 36 | 11-Aug-2006 |
| The Love/Hate Relationship with DDR SDRAM Controllers | MOSAID Virtual Silicon | 61 | 19-Jul-2006 |
| Has Your Known Good Die Died? | Inapac Technology Inc. | 17 | 18-Jul-2006 |
| Design Closure Crisis | Athena | 16 | 13-Jun-2006 |
| A 13 Weeks project in just 1 week, for less then $2K. | GIDEL | 53 | 01-May-2006 |
| A Dynamically Reconfigurable Processor for Dataflow Graph Execution. | GIDEL | 66 | 01-May-2006 |
| Rapid inductance modeling and netlist reduction boosts RFIC design | Edxact | 13 | 24-Apr-2006 |
| Recent Developments in Polyimide-Based Planar Capacitor Laminates | SIGRITY, Inc. | 23 | 13-Apr-2006 |
| 2003 IEEE JSSC Paper: Precise Delay Generation Using Coupled Oscillators | True Circuits, Inc. | 33 | 06-Mar-2006 |
| New Design Comprehension Solution: Visibility Enhancement Technology for Simulation, Emulation and Prototyping | Novas | 28 | 06-Mar-2006 |
| A Codeless BIST Processor for Embedded Test and insystem | Intellitech | 50 | 02-Mar-2006 |
| A Fast Access Controller for In-System Programming of FLASH Memory Devices | Intellitech | 20 | 02-Mar-2006 |
| An Embedded Test and Configuration Processor for Self-Testable and Field Re-Configurable Systems | Intellitech | 47 | 02-Mar-2006 |
| Infrastructure IP for Configuration and Test of Boards and Systems | Intellitech | 18 | 02-Mar-2006 |
| Infrastructure IP for Programming and Test of in-system Memory Devices | Intellitech | 25 | 02-Mar-2006 |
| A systematic development of virtual components compatible to standard ICs | Evatronix S.A. | 19 | 06-Feb-2006 |
| Developing the concept of hardware modeling to enhance verification process in virtual component design | Evatronix S.A. | 41 | 06-Feb-2006 |
| Developing the concept of hardware modeling to enhance verification process in virtual component design | Evatronix S.A. | 10 | 06-Feb-2006 |
| Development of a configurable microcontroller core | Evatronix S.A. | 35 | 06-Feb-2006 |
| Use of Multi-Phase Stability Intervals to handle Crosstalk with the Timing | Avertec Inc. | 64 | 10-Jan-2006 |
| YAGLE, a Second Generation Functional Abstractor for CMOS VLSI Circuits | Avertec Inc. | 96 | 10-Jan-2006 |
| SILICON DESIGN CHAIN EXTENDS LOW POWER DESIGN COLLABORATION | Cadence Design Systems, Inc. | 53 | 09-Jan-2006 |
| Biological Effects of Microwaves: Thermal and Nonthermal Mechanisms* | A Report by an Independent Investigator | 21 | 12-Dec-2005 |
| CADENCE PHYSICAL VERIFICATION SYSTEM | Cadence Design Systems, Inc. | 83 | 02-Dec-2005 |
| Shorten and Simplify SoC Verification using a Generic eVC | Verilab | 12 | 28-Nov-2005 |
| Extending the Utility of 3-D Package Models into the Gigabit Range | Optimal Corp. | 14 | 03-Nov-2005 |
| Muscular Methods for Mammoth Designs | VaST | 14 | 23-Sep-2005 |
| Altium Corporate Brochure | Altium | 18 | 20-Sep-2005 |
| So what use are FPGAs – really? | Altium | 129 | 20-Sep-2005 |
| An Alternative Approach to Circuit Design and Assembly for High Speed Interconnections | SiliconPipe, Inc. | 52 | 16-Aug-2005 |
| Silicon Design Chain collaboration extends 90-nanometer low-power design into the mainstream | Silicon Design Chain | 23 | 16-Aug-2005 |
| Comprehensive Solution Space Simulation and Analysis | SiSoft | 37 | 27-May-2005 |
| Design Analysis Reuse | SiSoft | 42 | 27-May-2005 |
| High-Speed Design Methodology | SiSoft | 207 | 27-May-2005 |
| Using VN-Spec™ with íManager™ | TransEDA | 31 | 14-Apr-2005 |
| A Fast Evaluation of Power Delivery System Input Impedance of Printed Circuit Boards with Decoupling Capacitors | SIGRITY, Inc. | 90 | 13-Apr-2005 |
| IR Drop in High-Speed IC Packages and PCBs | SIGRITY, Inc. | 125 | 13-Apr-2005 |
| On-Chip Power Integrity, Including Package Effects | SIGRITY, Inc. | 103 | 13-Apr-2005 |
| Transaction-Level Modelling and Debug of SoCs | Novas | 1 | 03-Jan-2005 |
| Transaction-Level Modelling and Debug of SoCs | Novas | 13 | 03-Jan-2005 |
| System/Circuit Design and Analysis of an IEEE 802.11a RF CMOS Transceiver | Applied Wave Research, Inc. (AWR) | 219 | 15-Dec-2004 |
| Using Visual System Simulator 2004 Delivers Unique New Technology for RF Budget Analysis | Applied Wave Research, Inc. (AWR) | 60 | 15-Dec-2004 |
| 64GHz and 100GHz VCOs in 90nm CMOS Using Optimum Pumping Method | Applied Wave Research, Inc. (AWR) | 78 | 01-Dec-2004 |
| CORDIC Algorithm Implemented as a Virtual Component | Evatronix S.A. | 233 | 26-Nov-2004 |
| Selecting PLLs for ASIC Applications Requires Tradeoffs | True Circuits, Inc. | 171 | 28-Oct-2004 |
| Mobilize - Power Islands: The Evolving Topology of SoC Power Management | Virtual Silicon | 110 | 27-Oct-2004 |
| Downstream Thermal Implications of Component Placement | Flomerics | 23 | 10-Aug-2004 |
| Ten Steps to a Successful DSP Core Integration | StarCore | 99 | 04-Jun-2004 |
| Going Beyond 32-bit - EDA Linux Computing | hp | 218 | 12-Apr-2004 |
| 2003 IEEE JSSC Paper: Self-Biased High-Bandwidth Low-Jitter 1-to-4096 Multiplier Clock Generator PLL | True Circuits, Inc. | 200 | 09-Apr-2004 |
| Crossing the Abyss | Paradigm Works Inc. | 57 | 06-Apr-2004 |
| ISSCC 24.2 slides | True Circuits, Inc. | 72 | 15-Jul-2003 |
