| Title |  |  |
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| Company | | |
| Views |
| Added | | |
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| IDaSS Popular | N/A | 487 | 22-Sep-2008 |
| A Generic and Reusable VMM Based CPU Verification Environment in SystemVerilog Popular | Synopsys Inc. | 135 | 28-Sep-2006 |
| Automated FFT RTL Creation using Verilog with Matlab and Perl Popular | Synopsys Inc. | 181 | 28-Sep-2006 |
| Berkeley's Design Technology Warehouse Popular | UC Berkeley Design Technology Warehouse | 3562 | 22-Dec-2005 |
| Differential Impedance Calculator Popular | In-Circuit Design Pty Ltd | 408 | 30-Jun-2004 |
| Multifunction Desktop Calculator Popular | IBSystems, Inc. | 629 | 25-Jun-2004 |
| Neanderthal Design (GdsDump) Popular | Neanderthal Design | 1170 | 22-Sep-2003 |
| The Event Controlled Systems Group's Tools Popular | N/A | 957 | 22-Sep-2003 |
| GDSII Viewer Popular | EDA Utilities | 622 | 05-Jul-2003 |
| TimingTool Popular | TimingTool | 727 | 20-Apr-2003 |
| SAVANT Popular | Clifton Labs Inc | 756 | 25-Sep-2001 |
| savant-2.0-pre010829.tar.gz Popular | Clifton Labs, Inc. | 690 | 05-Sep-2001 |
| TCAD Tools Popular | N/A | 661 | 22-Sep-1999 |
| WaferMap Popular | BOIN Scientific Software | 859 | 22-Sep-1999 |
| Sigasi 2.0 Starter Edition | Sigasi | 1 | 19-Aug-2011 |
| UVM Reference Flow Overview | Cadence Design Systems, Inc. | 9 | 02-Jan-2011 |
| Test-driven design, a methodology for low-defect software | Olivier Coudert | 0 | 22-Oct-2009 |
| API Design 101 | Olivier Coudert | 8 | 09-Oct-2009 |
| Electronic System Level (ESL) Debug -- Trends, Requirements, and Technology | SpringSoft, Inc. | 26 | 27-Sep-2009 |
| Sigasi HDT | Sigasi | 0 | 23-Sep-2009 |
| IP Return on Investment (ROI) Calculator | Mentor Graphics | 15 | 06-Apr-2009 |
| SEICA shows how VIVA extend test coverage of complex boards with DiaTem JTAG tool | TEMENTO Systems | 7 | 28-Dec-2008 |
| GBL Design Studio 2.0 | GB Research LLC | 13 | 20-Oct-2008 |
| DataSheet Pro - professional data book documentation tool | SynaptiCAD, Inc. | 28 | 26-Jun-2008 |
| TestBencher Pro - system level verification tool | SynaptiCAD, Inc. | 30 | 26-Jun-2008 |
| Timing Diagrammer Pro - Timing Diagram Editor | SynaptiCAD, Inc. | 18 | 26-Jun-2008 |
| Verilog2VHDL and VHDL2Verilog - hdl translation tools and services | SynaptiCAD, Inc. | 98 | 26-Jun-2008 |
| VeriLogger Extreme - Verilog Simulator | SynaptiCAD, Inc. | 25 | 26-Jun-2008 |
| WaveFormer Pro - timing diagram editor and waveform translator | SynaptiCAD, Inc. | 16 | 26-Jun-2008 |
Dane Collins
Chief Executive Officer | AWR Corporation | 66 | 09-May-2008 |
| vericnet, netlist comparator | VerIC Systems LLC | 22 | 11-Apr-2008 |
| OCP Debug Socket for Multi-Core Debugging | OCP International Partnership (OCP-IP) | 13 | 16-Mar-2008 |
| Standard Debug Interface Socket Requirements For OCP-Compliant SoC | OCP International Partnership (OCP-IP) | 7 | 16-Mar-2008 |
| Lauro Rizzatti, Vice President of Marketing, GM | EVE USA Inc. | 63 | 13-Feb-2008 |
| Using Assertion Based Verification in a Refinement Driven Design Flow | Fraunhofer Institute for Integrated Circuits | 32 | 01-Dec-2007 |
| Multi-FPGA Prototyping using DC FPGA | Fraunhofer Institute for Integrated Circuits | 22 | 18-Nov-2007 |
| 500 Mb/s DDR2 SDRAM Analysis using HSPICE® | Broadcom Corporation | 44 | 30-Sep-2007 |
| A Fast Methodology for Setup/Hold Time Characterization of Analog IPs | Faraday Technology | 22 | 30-Sep-2007 |
| A near at-speed non-pipelined BIST Compiler for Dual Port Embedded Memories using Synopsys Synthesis flow | Philips Semiconductors | 17 | 30-Sep-2007 |
| Assertion Based Verification, Checkers and Smart Lint | Intel | 34 | 30-Sep-2007 |
| AstroRail Power Gating Analysis using Switch Cell Methodology | Intel | 36 | 30-Sep-2007 |
| Building reusable, random constraint based, and coverage driven Verification IPs | Arnon Verification Ltd | 17 | 30-Sep-2007 |
| Distributed Full System Simulation Using SystemC | Dune Networks | 17 | 30-Sep-2007 |
| Fighting Scan Test Time and Data Volumes; Squeezing the last drop out of DFT Compiler and TetraMAX? | Nordic Semiconductor ASA | 14 | 30-Sep-2007 |
| From RDB to SoC Verification | Wisair | 7 | 30-Sep-2007 |
| Functional Verification of DVBS2 Receiver ASIC using RVM | Efficient Channel Coding, Inc. | 19 | 30-Sep-2007 |
| HSIM’s Integration within ST Design Flow for Smart Power and High Voltage technologies | STMicroelectronics | 24 | 30-Sep-2007 |
| Linking The Tools Chain In Synopsys flow | Tower Semiconductor LTD | 21 | 30-Sep-2007 |
| Low Power Design Methodology | CEVA | 63 | 30-Sep-2007 |
| Margin Selection Criteria for Area and Dynamic Power Reduction | Texas Instruments Inc. | 24 | 30-Sep-2007 |
| Migrating to DFT Max | STMicroelectronics | 21 | 30-Sep-2007 |
| Monte Carlo Statistical Analysis for Dynamic Power Simulation of RTL Designs using Synopsys Power Compiler | Nanyang Technological University | 23 | 30-Sep-2007 |
| POWER ANALYSIS FLOW FOR SoC | STMicroelectronics | 48 | 30-Sep-2007 |
| Power Estimation Methodology using Nanosim | Intel Corporation | 40 | 30-Sep-2007 |
| Rapid Static Timing Analysis with ILM | Intel Corporation | 44 | 30-Sep-2007 |
| Standard Gotchas - Subtleties in the Verilog and SystemVerilog Standards That Every Engineer Should Know | Sutherland HDL, Inc. | 51 | 30-Sep-2007 |
| Synthesizing Asynchronous Micropipelines with Design Compiler | Boston University | 23 | 30-Sep-2007 |
| Unified Functional Verification Approach for GPON SoC Application | Intrinsix | 13 | 30-Sep-2007 |
| Using RVM to Verify WIMAX Modem | Alvarion | 12 | 30-Sep-2007 |
| VMM For Dummies | XtremeEDA Corporation | 71 | 30-Sep-2007 |
| Budget Timing Constraint Generation by Post-Processing PrimeTime Results | Hewlett Packard | 32 | 29-Sep-2007 |
| From Libraries to Implementation: An IP Analysis and Mixed-Vt Methodology | The MITRE Corporation | 8 | 29-Sep-2007 |
| Integration of a datapath generation with an ASTRO flow | Nova Semiconductor | 19 | 29-Sep-2007 |
| Power Reduction through Channel Length Optimization and Clock Gating using Power Compiler | Intel Corporation | 31 | 29-Sep-2007 |
| Taming the �Congestion� Beast � Methods to Handle Congestion during Physical Design Implementation | QUALCOMM, Inc. | 31 | 29-Sep-2007 |
| Basic Characterization Analog IP | Faraday Technology | 17 | 28-Sep-2007 |
| Interfacing C Functional Verification Stimuli with Verilog, OpenVera and SystemVerilog | Freescale Semiconductor Inc. | 41 | 28-Sep-2007 |
| Using SVA with VCS for Mixed-Language Verification | Fraunhofer Institute for Integrated Circuits | 20 | 28-Sep-2007 |
| An Integrated SystemC/Verilog RTL Simulation Infrastructure for Co-simulation of ESL Models | Synfora Inc. | 56 | 27-Sep-2007 |
| Achieving Web Acceleration through Hardware Compression | Comtech AHA Corp | 3 | 25-Aug-2007 |
| PCI Bridge Verification with Concurrent Stimulus Threads on a Reusable Testbench Architecture | Freescale Semiconductor Inc. | 22 | 17-Aug-2007 |
| Batelco, Bahrain, develops a comprehensive 3G strategy | LM Ericsson | 2 | 23-Mar-2007 |
| CANopen | Sontheim Industrie Elektronik GmbH | 11 | 20-Feb-2007 |
| A Case Study of Hierarchical Scan Compression Implementation Using Synopsys' DFT MAX | Synopsys Inc. | 63 | 30-Sep-2006 |
| Five Keys to Predictability | ACE Verification | 11 | 30-Sep-2006 |
| Technique for Optimizing IBM® Power PC 440 Cache SRAM Clock Latency for Highest Performance | Synopsys Inc. | 36 | 30-Sep-2006 |
| The Congestion Dragon Can be Defeated. Fighting Congestion Techniques with Physical Compiler® | Synopsys Inc. | 40 | 30-Sep-2006 |
| Aggressive Leakage Management in ARM Based Systems | Synopsys Inc. | 39 | 29-Sep-2006 |
| Analysis of Accuracy vs. Runtime/Memory Tradeoffs in PrimeTime SI | Synopsys Inc. | 66 | 29-Sep-2006 |
| Automated Response Generation for IP Based Subsystem Verification | Synopsys Inc. | 25 | 29-Sep-2006 |
| Automating Formal Methods to Verify SoC Padring Integration | Synopsys Inc. | 41 | 29-Sep-2006 |
| Fault Simulation of Non-Scan Designs with Delays | TATA ELXSI LIMITED | 16 | 29-Sep-2006 |
| Methodology to Analyze and Insert a Power Mesh Early in Design Cycle | Synopsys Inc. | 75 | 29-Sep-2006 |
| Predicting Chip-Package Resonance of the Power Distribution Network Using PrimeRail | Synopsys Inc. | 49 | 29-Sep-2006 |
| Using Distributed Multi-Scenario Analysis to Dramatically Improve the PrimeTime Timing ECO Flow | Synopsys Inc. | 73 | 29-Sep-2006 |
| Leda Use in Industry: Design Quality Improvements and Proprietary System Integration | Synopsys Inc. | 29 | 28-Sep-2006 |
| Static Power Net Integrity Analysis on STMicroelectronics Set Top Box Products | Synopsys Inc. | 32 | 28-Sep-2006 |
| High Speed Serial Interconnects - What to Look for When Selecting an IP Vendor | Synopsys Inc. | 26 | 27-Sep-2006 |
| Integrating DesignWare Digital IP Core for PCI Express into Agere’s ET1310 Gigabit Ethernet Controller | Synopsys Inc. | 13 | 27-Sep-2006 |
| Integrating System Models in an RVM Leveraged Environment | Synopsys Inc. | 15 | 27-Sep-2006 |
| System Verilog constraints for assertion-based formaln verification | Synopsys Inc. | 102 | 27-Sep-2006 |
| GdsViewer 2.1 | GB Research LLC | 58 | 31-Jul-2006 |
| GDS Utilities | GB Research LLC | 56 | 29-Mar-2006 |
| TimeGen Timing Diagram Editor | XFusion Software | 64 | 16-Mar-2006 |
| LDTViewer | LSYMTech | 22 | 01-Sep-2005 |
| Kernel Linux - Data Recovery Software | Nucleus Technologies.com | 7 | 11-Aug-2005 |
| InCyte - Free Chip Estimation Tool | Giga Scale | 34 | 03-Mar-2005 |
| LIBedit - EDA Library Manager | LIBedit | 81 | 25-Jun-2004 |
| InnerLoop for Solaris, Linux, and Windows | Posedge Software | 55 | 09-Jun-2004 |
| Micro-VCap 8 Demo Version | Spectrum Software | 65 | 06-Apr-2004 |
| IBIS Development Studio | Edality | 90 | 02-Mar-2004 |
| VisualSpice Advance Mixed Mode Simulator | Island Logix | 187 | 02-Mar-2004 |
| Mac's Verilog Mode for emacs | Verisity, Inc. | 292 | 22-Jan-2004 |
| VisualSpice | Island Logix | 203 | 01-Dec-2003 |
| Eko Design Compiler | Intrada-SDD Ltd | 43 | 07-Aug-2003 |
| PCB123- the PCB Design-to-Order Software | PCB123 | 35 | 07-Aug-2003 |
| LayView | SSA SoftSolutions GmbH | 138 | 05-Jul-2003 |
| Anatomy of a Signal Integrity Failure | IBM Engineering and Technology Services | 252 | 06-Feb-2003 |
| VHDL to Verilog RTL translator | Ocean Logic Pty Ltd | 378 | 06-Mar-2001 |
| hbfree-0.1.tar.gz | Gennady Serdyuk | 101 | 05-Dec-2000 |
| BSIM4 | University of California, Berkeley | 276 | 12-Jun-2000 |
| Ballistic | gdt@eecg.toronto.edu | 278 | 22-Sep-1999 |
| Bsim3 | University of California, Berkeley | 406 | 22-Sep-1999 |
| Carafe | Regents of the University of California | 161 | 22-Sep-1999 |
| Chipmunk Tools | UC Berkeley/CS Division | 355 | 22-Sep-1999 |
| Nemesis | N/A | 236 | 22-Sep-1999 |
| Power Optimization and Synthesis Environment (POSE) | N/A | 298 | 22-Sep-1999 |
| Sunsite's /pub/Linux/apps/circuits directory. | Sunsite | 290 | 22-Sep-1999 |
| Voyeur | N/A | 410 | 22-Sep-1999 |
