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ncreasing pressure on production costs and, more generally, time to market, have impacted all levels of IC design. In this context, one of the major challenges is to avoid silicon failure or yield loss. Indeed, a widely accepted statistic today is that almost half of all designs fail at first silicon. Failure costs are obviously due to new mask generations, and additional engineering time, but also to the potential miss of a large part of the market window for a product. Therefore, first-pass silicon success and high design yield has become a fundamental requirement for IC designs, and is, quite naturally, driving an increasing need for integrated circuit verification and debugging solutions. Debugging is a methodical process of finding and reducing the number of defects. Thus, any software solution will never replace the designer's know-how. Nevertheless, to assist designers in this cumbersome task, the goal of the debugging solutions is to identify defects before silicon runs. In this article, we report how the use of appropriate CAD solutions helps us design a high-resolution ADC good in first silicon pass.
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