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Title : A Smart Synchronizer - Pragmatic way to cross asynchronous clock domains.
Company : DVCon 2011
File Name : 06_1.pdf
Size : 137689
Type : application/pdf
Date : 22-Mar-2011
Downloads : 57

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Featured Paper by Priyank Parakh & Steven J Kommrusch

In order to achieve satisfactory verification coverage in an asynchronous design, it is highly desirable to model a synchronizer with all the checks that can help catch the problem. Modeling uncertainty caused by metastable values at the output of the synchronizer is one of them.
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