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Title : A Practical Look @ SystemVerilog Coverage – Tips, Tricks, and Gotchas
Company : DVCon 2011
File Name : 01P_1.pdf
Size : 237592
Type : application/pdf
Date : 19-Mar-2011
Downloads : 30

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Featured Paper by Doug Smith & John Aynsley



Functional verification of today’s large and complex designs is a major challenge and bottleneck. As a result, various tools, techniques, and languages have been developed to automate as much as possible to maximize productivity. For example, automatic testbench generation of random stimulus offers a significant aid in finding obscure and hard-to-find bugs.
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