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Featured Paper by Amit Sharma, Abhisek Verma, Varun S & Anoop Kumar In a few weeks, the Accellera VIP TSC will release the "1.0" version of the Universal Verification Methodology (UVM). This was the next step for the committee after it had released the UVM EA release early last year This has been quite significant because, the three major verification vendors have aligned on a single SystemVerilog Base-Class Library and Methodology for the first time.
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