Automated approach to Register Design and Verification of complex SOC - EDACafe Downloads

All Categories : Technical Papers : DVCon 2011

Featured Paper by Ballori Banerjee , Subashini Rajan & Silpa Naidu

Today's designs contain several hundreds to thousands of registers and memory elements. Starting from documentation to design implementation to verification of each single register, each bit and its property involves a lot of time and complexity.

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